High-NA EUV Enters the Battlefield: The Lithography Equipment Race in the Angstrom Era

Foreword: The Angstrom Frontier and the $400 Million "Shovel"

As the semiconductor industry steadfastly advances beyond the nanometer scale, a more precise competition has begun on the "Angstrom" frontier. The industry is actively challenging unprecedented process nodes like A14 (1.4 nm) and A10 (1.0 nm), where the continuation of Moore's Law faces the severe test of physical limits. In this race, the most critical tool, the most expensive "shovel," is undoubtedly the High-Numerical Aperture Extreme Ultraviolet (High-NA EUV) lithography system from the Dutch equipment giant, ASML.   

This article aims to provide an in-depth analysis of this epoch-making technological shift. High-NA EUV is not merely an incremental upgrade to existing EUV technology; it represents a paradigm shift, offering a simplified, higher-resolution patterning path for several future generations of chip manufacturing. However, this path is fraught with immense financial risks and technical challenges. The staggering price of $380 million to $400 million per system forces foundry leaders to make difficult choices in their investment strategies. This has sparked a core debate: should the industry embrace the single-exposure simplicity of High-NA EUV, or continue to rely on existing Low-NA EUV equipment for more complex, but potentially more cost-effective, multi-patterning? The divergent strategies adopted by industry giants like Intel, TSMC, and Samsung represent a high-stakes gamble that will shape the semiconductor landscape for the next decade. The outcome of this race depends not only on ASML's equipment but also on the synchronized evolution of the entire semiconductor ecosystem—from photomasks and photoresists to thin films and inspection technologies, every link in the chain must overcome unprecedented challenges.   

A Technological Leap: Deconstructing High-NA EUV

To understand the strategic divergence and economic debate sparked by High-NA EUV, one must first delve into its technological core. This is not just a specification upgrade but a series of ingenious engineering designs and compromises born from the need to solve fundamental physical problems.

From 0.33 to 0.55 NA: A Revolution in Resolution

The core breakthrough of High-NA EUV technology lies in the significant increase of its optical system's Numerical Aperture (NA). NA is a physical quantity that measures an optical system's ability to collect and focus light. ASML's current standard EUV systems used in mass production (like the TWINSCAN NXE series) employ a 0.33 NA optical design, with a theoretical resolution limit of about 13 nm. However, as process nodes advance below 2 nm, the industry needs the ability to directly image finer circuit patterns.   

To this end, ASML and its optical partner ZEISS developed the new EXE system with a 0.55 NA. This leap pushes the theoretical resolution to 8 nm. This 8 nm capability is considered key to achieving single-exposure for critical layers in the angstrom era, thereby avoiding complex and costly multi-patterning processes.   

The price of achieving this goal is an immense engineering challenge. To capture light at wider angles, the size of the new system's mirrors had to be substantially increased, causing the entire optical system to expand dramatically. A High-NA EUV system's projection optics module consists of over 40,000 parts and weighs 12 tons, while the illumination system is composed of over 25,000 parts and weighs more than 6 tons. Overall, the High-NA optical system is about seven times larger in volume and weight than the previous 0.33 NA generation. This is not just a technological upgrade but a challenge to the limits of precision mechanical engineering and manufacturing.   

The Anamorphic Optics Compromise: ASML's Ingenious Optical Solution

The giant mirrors required to increase the NA directly led to a tricky physical problem. In an all-reflective optical system like EUV, light illuminates a reticle (or photomask) at a specific angle, and the circuit pattern is then reflected by the reticle into the projection optics. The larger mirrors of the 0.55 NA system cause the chief-ray-angle of the light hitting the reticle to become too large. At this angle, the multilayer mirror on the reticle's surface loses its reflective efficiency, preventing the pattern from being effectively transferred and causing the lithography process to fail.   

Faced with this dilemma, there were two theoretical solutions: double the reticle size or change the optical design. The former would force a costly and time-consuming overhaul of the entire reticle manufacturing, inspection, and transport infrastructure, with a massive impact on the industry ecosystem. Therefore, ASML and ZEISS chose the latter, proposing a highly creative solution: anamorphic optics.   

The core of this design is an asymmetric demagnification. Traditional lithography machines demagnify the pattern on the reticle by a factor of 4 in both the X and Y directions. The High-NA anamorphic optical system, however, maintains a 4x reduction in one direction (slit) but uses an 8x reduction in the other (scan). This clever 4x/8x asymmetric design effectively reduces the range of incident angles on the reticle, solving the reflectivity problem and allowing fabs to continue using the industry-standard 6-inch reticle.   

However, this ingenious solution brings an unavoidable consequence: the single-exposure field size on the wafer is reduced to half that of a standard 0.33 NA system. This "half-field" characteristic introduces a new "stitching" challenge for the design and manufacturing of large-sized chips, which we will explore in the following chapter.   

Engineering for Productivity: The Pursuit of Over 200 Wafers Per Hour

A halved exposure field means that twice the number of exposures are needed to pattern a single wafer. Without other compensatory measures, this would directly cut productivity in half, severely impacting the economic viability of High-NA technology.   

To overcome this productivity bottleneck, ASML engineers developed extremely fast wafer and reticle stages. The wafer stage in the EXE system has an acceleration of up to 8g, double that of the previous-generation NXE system. The reticle stage's performance is even more astounding, with an acceleration of 32g, four times that of the NXE system, equivalent to a race car accelerating from 0 to 100 km/h in 0.09 seconds.   

Thanks to these ultra-fast stages, the throughput of the TWINSCAN EXE:5000 model can exceed 185 wafers per hour (WPH), even surpassing some NXE systems already in mass production. ASML's technology roadmap plans to increase throughput to 220 WPH by 2025. ASML has even proposed future throughput targets of 400 to 500 WPH to further reduce the cost per wafer exposure. Such high production efficiency is seen by ASML as a key pillar to ensure that fabs can maintain economic benefits when adopting High-NA technology.   

An Interlocking Series of Trade-offs: The Inherent Logic of High-NA Design

In summary, the overall architecture of High-NA EUV is not a "no-compromise" technological leap but a collection of interlocking trade-offs and ingenious engineering solutions. Its development logic clearly demonstrates the complexity of semiconductor equipment development:

1. Primary Goal: Pursue higher resolution (8 nm), which physically requires a higher numerical aperture (0.55 NA).

2. Resulting Problem: Higher NA requires larger mirrors, which creates a physical problem at the reticle—reflectivity failure due to excessive incident angles.

3. Optical Solution: To solve the reflectivity problem while preserving the existing reticle infrastructure, anamorphic optics (4x/8x reduction) were developed.

4. New System Problem: Anamorphic optics, however, introduced a new system-level issue—a halved exposure field, which directly threatened the tool's productivity and economic viability.

5. Mechatronic Solution: To solve the productivity problem, ultra-fast stages were developed, compensating for the doubled number of exposures with incredible acceleration.

6. Final Challenge: Although the productivity issue was resolved, the half-field characteristic left an unavoidable consequence—large chips require "stitching." This introduces new complexities and potential error sources (like overlay accuracy, critical dimension uniformity) for process control, becoming a new challenge that the entire ecosystem must solve together.

This chain of cause and effect reveals that the success of High-NA is not as simple as ASML building the machine. It relies on the entire industry chain adapting to and solving the downstream challenges derived from its core design. For investors, this means that risk is not concentrated in ASML alone but is distributed across the entire ecosystem, where a bottleneck in any single link could affect the whole picture.

The Billion-Dollar Gamble: Strategy and Cost-Benefit Analysis

While the technological breakthrough of High-NA EUV is remarkable, its high cost and uncertain return on investment are sparking a fierce debate in the industry, driving the three major foundry giants down distinctly different strategic paths.

The Staggering Price Tag: The Cost Impact of High-NA

The price tag for a High-NA EUV system is daunting. According to industry reports, each system costs between $380 million and $400 million , more than double the price of the latest generation Low-NA EUV tools, which cost about $180 million to $200 million.   

This is not just the procurement cost of a single piece of equipment; it will have a profound impact on the capital expenditure (CapEx) model of a fab. An advanced process fab requires dozens of lithography tools to maintain capacity. To fully equip a new fab with High-NA technology, the investment in lithography equipment alone would amount to billions of dollars, completely changing the financial model and risk assessment for fab construction.   

The Core Debate: High-NA Single Exposure vs. Low-NA Multi-Patterning

The main justification for the high price of High-NA is the "process simplification" it brings. By completing patterns in a single exposure that would otherwise require complex multi-patterning (such as double or quadruple patterning) with Low-NA EUV, High-NA promises to significantly reduce production steps and shorten manufacturing cycles. More importantly, it can reduce overlay errors and the chances of defect generation common in multi-patterning, thereby improving yield.   

However, a powerful counterargument is challenging this assumption. Citing research data from industry analysis firm SemiAnalysis and IBM, the core argument revolves around the relationship between "dose" and throughput. The relationship between Critical Dimension (CD) and the required exposure dose is exponential: the finer the pattern, the higher the photon energy required.   

• High-NA's Dilemma: Since High-NA throughput is often limited by dose, to print the finest patterns, the equipment must slow down its scan speed to accumulate enough energy. This directly reduces the wafer output per unit of time, driving up the cost per wafer.   

  
  

• Low-NA's Advantage: In contrast, Low-NA double patterning splits a complex pattern onto two masks, with each exposure handling a pattern with looser lines and spaces. This significantly reduces the dose required for each exposure, allowing the machine to operate at its maximum mechanical speed, thus maximizing throughput.   

  
  

The conclusion based on this model is that a single High-NA exposure costs about 2.5 times as much as a single Low-NA exposure. This means that    

High-NA only starts to become cost-effective when it can replace a process step that requires at least three or more Low-NA exposures. If it can replace a complex four-mask process, its cost advantage becomes significant, reaching 1.7 to 2.1 times.   

Table 1: Per-Wafer Lithography Cost Model Comparison (High-NA vs. Low-NA Multi-Patterning)

Number of Low-NA Exposures Replaced	Example Process Scenario	Relative Cost of Low-NA Multi-Patterning	Relative Cost of High-NA Single Exposure	High-NA Cost Advantage/(Disadvantage)
1 Pass	Relaxed pitch layer	1.0x	~2.5x	(1.5x) Cost Disadvantage
2 Passes (Double Patterning)	Advanced metal layer (30nm pitch)	2.0x	~2.5x	(0.5x) Cost Disadvantage
3 Passes (Triple Patterning)	Very dense metal layer (21nm pitch)	3.0x	~2.5x	0.5x Cost Advantage
4 Passes (Quadruple Patterning)	Future very dense metal layer	4.0x	~2.5x	1.5x Cost Advantage

Note: This is a simplified model based on public research data. Actual costs are affected by numerous factors including dose, overlay, etch, etc. Relative cost is based on a single Low-NA exposure as a 1.0x baseline.

Strategic Divergence: The Big Three's Gamble of the Century

This cost-benefit debate has directly led to a major divergence in the High-NA adoption strategies of the three major foundry giants.

• Intel's Aggressive Gamble: Intel is the most aggressive proponent of High-NA, not only being the first customer to place an order but also rumored to have secured all five High-NA systems produced by ASML in 2024. For Intel, this is a strategic necessity. CEO Pat Gelsinger has admitted that past hesitation in adopting EUV technology was a key mistake that led to its foundry business falling behind. Therefore, Intel's bet is that by being the first to master High-NA technology, it can achieve a technological leapfrog at the 14A node and reclaim process leadership. For this, they are willing to bear higher initial costs and potential loss risks.   

  
  

• TSMC's Pragmatic Caution: As the market leader, TSMC's attitude towards High-NA appears pragmatic and cautious. Its Senior Vice President of Business Development, Kevin Zhang, once stated clearly: "I like its performance, but I don't like its price". TSMC has decided to continue using its existing Low-NA EUV equipment for its A16 process node and may even extend this strategy to the A14 node. They aim to provide the most cost-effective solutions for their customers by leveraging their deep experience and economies of scale in multi-patterning technology. TSMC's strategy is to wait for High-NA technology to mature and for the cost-benefit curve to clearly invert before adopting it.   

  
  

• Samsung's Balanced Approach: Samsung has taken a middle path. On one hand, it is actively purchasing High-NA equipment for R&D at its new semiconductor research center in Korea (NRD-K), with the goal of applying it to 1.4 nm logic processes. On the other hand, Samsung is reserved about introducing High-NA into its DRAM business, as future 3D DRAM architectures may no longer rely on EUV lithography, making the huge investment a potential burden. This dual-track strategy reflects Samsung's need to hedge risks across different business units as a comprehensive enterprise spanning both logic foundry and memory markets.   

Market Positioning Behind the Strategies

The strategic divergence of the big three is not just a choice of technology routes but a direct reflection of their respective market positions and core competencies.

• Intel: As a challenger trying to reclaim the throne, Intel must adopt a high-risk, high-reward offensive strategy. It cannot win by imitating TSMC's incremental optimization; only by launching a disruptive technological leap can it possibly change the competitive landscape. For Intel, the financial risk of early adoption is far less than the strategic risk of continuing to lag.

• TSMC: As the leader with a vast customer base and a highly efficient production system, TSMC's primary task is to ensure stability, predictability, and cost-effectiveness. Its strategy is defensive, aimed at maximizing the utilization of its tens of billions of dollars in Low-NA equipment assets to provide customers with the lowest-risk, highest-return service. It will only adopt High-NA on a large scale after it becomes a low-risk, high-return mature technology.

• Samsung: As an integrated enterprise fighting on both the foundry and memory fronts, Samsung's strategy is necessarily more complex. It must invest in High-NA to catch up with TSMC in the AI chip foundry space , while also being wary that the technology may have limited applicability to its future memory roadmap (3D DRAM). Its balanced strategy seeks the optimal equilibrium between the uncertainties of its different business divisions.   

  
  

Ultimately, the winner of the High-NA race will not be just the first adopter, but the company whose adoption strategy best fits its own business model and market position. The outcome of this race will profoundly reshape the semiconductor industry landscape for the next decade.

Ecosystem Challenges: Hurdles on the Road to Mass Production

ASML's successful delivery of the High-NA EUV scanner is just the first step on a long journey. To truly put this technology into High Volume Manufacturing (HVM), the entire semiconductor ecosystem—from materials and masks to inspection—must undergo a synchronized and arduous technological revolution.

The Photoresist Trilemma: Navigating the RLS Triangle in an Ultra-thin World

While High-NA brings higher resolution, it also significantly reduces the Depth of Focus (DoF), an inherent physical characteristic of high-numerical-aperture optical systems. To ensure that patterns are precisely focused on the wafer, extremely thin photoresist films must be used.   

This ultra-thin photoresist layer plunges material scientists into the classic "RLS triangle" trade-off dilemma: balancing Resolution, Linewidth Roughness (LWR), and Sensitivity. As the resist layer thins, the number of EUV photons it can absorb decreases, which exacerbates "stochastic defects" caused by the random distribution of photons, leading to rougher line edges (worsening LWR). In traditional Chemically Amplified Resists (CARs), improving one of these parameters often requires sacrificing the other two.   

To address this, the industry is accelerating the development of new-generation photoresist materials. New technologies like Metal Oxide Resists (MORs) and dry resists are gaining attention for their potential in high resolution and low roughness, but they also bring new process integration and etching challenges. The ecosystem is still searching for the optimal solution.   

Masks and Membranes: The Complexity of Anamorphic Optics and the Urgent Need for Pellicles

• Anamorphic Mask Manufacturing Challenges: The 4x/8x anamorphic optical design introduces new complexities to mask manufacturing. The traditional Mask Error Factor (MEF) needs to be redefined, and manufacturing rule checks (MRC) must consider the orientation of patterns. Furthermore, due to the extremely small DoF at the wafer level, controlling Mask 3D effects (like shadowing) has become more critical than ever.   

  
  

• Pellicle Challenges: A pellicle is an ultra-thin transparent membrane mounted over the reticle to protect the delicate pattern from particle contamination, a key component for ensuring high-yield mass production. For High-NA EUV and future higher-power (>600W) light sources, the pellicle must meet extremely demanding conditions simultaneously: extremely high EUV transmittance (>90%), excellent thermal resistance (withstanding temperatures up to 800°C or even higher), and mechanical strength under high acceleration.   

  
  

• Carbon Nanotubes (CNT) as a Solution: Traditional silicon-based materials can no longer meet these requirements. Carbon nanotubes (CNT) have become the most promising next-generation pellicle material due to their unique physical properties—combining high strength, excellent thermal resistance (stable up to 1500°C in a vacuum), and extremely high EUV transmittance (experimental data shows 97-98%). Material suppliers like Japan's Mitsui Chemicals are collaborating with top research institutions like imec to commercialize CNT pellicles within the 2025-2026 timeframe to support the mass production adoption of High-NA EUV.   

The Stitching Seam: Overcoming Half-Field Limitations

As mentioned earlier, anamorphic optics result in a High-NA exposure field that is only half the standard size (approx. 26mm x 16.5mm). For large chips exceeding this size (such as high-end CPUs and GPUs), two or more masks must be used to seamlessly "stitch" their patterns together on the wafer.   

This is an extremely challenging process control problem. It requires extremely high overlay accuracy between different exposure fields and ensuring that the critical dimension (CD) at the "seam" transitions smoothly to avoid creating a continuous defect band. Research institutions like imec are working closely with ASML and mask shops to develop "at-resolution stitching" technology and more advanced optical proximity correction (OPC) models to accurately predict and compensate for the optical interactions at the stitching boundary, minimizing their impact on circuit performance.   

The Inspection Frontier: Seeing the Nanoscale in a Low-Signal World

When pattern sizes shrink to 8 nm and resist layers are only tens of nanometers thick, traditional metrology and inspection tools face unprecedented challenges.

• Limits of Traditional Tools: The wavelength of traditional optical inspection tools is much larger than the features to be inspected, making their resolution insufficient to find nanoscale defects. Standard critical dimension scanning electron microscopes (CD-SEMs) face a low signal-to-noise ratio (SNR) dilemma due to the reduced electron beam interaction volume in ultra-thin resists, making it difficult to form clear images. Additionally, the high-energy electron beam itself can damage the fragile photoresist, causing measurement distortion.   

  
  

• The Rise of New Technologies: To meet these challenges, a new generation of inspection technologies has emerged:

  • Multi-Beam E-beam Inspection: To overcome the slow speed of traditional single-beam e-beam inspection, companies like ASML (HMI), KLA, and Applied Materials are developing multi-beam systems. These systems use hundreds of parallel electron beams to scan the wafer simultaneously, increasing inspection throughput by several to tens of times, making them suitable for real-time process monitoring on the production line.   

    
    

  • Advanced CD-SEM: Applied Materials' VeritySEM 10 system is a new-generation CD-SEM designed for the High-NA era. It uses a unique architecture to achieve 2x better resolution at low landing energies than conventional equipment, enabling precise measurement without damaging the photoresist.   

    
    

  • Scanning Probe Microscopy (SPM): SPM (or Atomic Force Microscopy, AFM) has a natural advantage in measuring ultra-thin, low-aspect-ratio structures. Although traditionally too slow for mass production, new high-throughput, multi-probe SPM systems are being developed as a key complementary metrology tool, capable of providing reference-grade, precise data on the topography of thin resists.   

    
    

Table 2: Comparison of Advanced Metrology Solutions for High-NA EUV

Metrology Technology	Resolution Capability (nm)	Relative Throughput	Thin Resist Applicability	Primary Application	Key Suppliers
Traditional CD-SEM	~2-3	Medium	Low	R&D, legacy process control	AMAT, KLA
Advanced CD-SEM (e.g., VeritySEM 10)	~1-1.5	Medium-High	High	In-line process control, 3D structure metrology	Applied Materials
Multi-Beam E-beam Inspection	~1-2	High	High	Large area defect inspection, in-line monitoring	ASML/HMI, KLA
High-Throughput SPM/AFM	<1 (Reference-grade)	Low	Very High	R&D, process development, reference data creation	Bruker, Park Systems

Note: Throughput and applicability are relative comparisons. Sources:    

The Ecosystem as a Key Limiting Factor

The timeline for the successful mass production adoption of High-NA EUV is not solely determined by the speed at which ASML delivers the machines. The more critical limiting factor is whether the entire ecosystem—materials, masks, inspection—can mature in sync.

We can clearly see the dependencies:

1. Even if a High-NA scanner is installed in a fab (as in Intel's case), it cannot operate stably at its target throughput without a qualified pellicle that can withstand the high-power light source.   

   
   

2. Even with a pellicle, if there is no photoresist that can stably resolve 8 nm patterns in an ultra-thin film without generating a large number of stochastic defects, it cannot produce high-yield wafers.   

   
   

3. Even if the first two are in place, if there are no inspection tools that can quickly and accurately measure the output patterns to provide process feedback, the production line cannot perform effective quality control.   

   
   

Therefore, a delay or failure in any part of the ecosystem will become a bottleneck for the entire industry roadmap, no matter how ready the scanner itself is. For investors, this highlights a new set of key companies to watch closely. The success of material suppliers (like Mitsui Chemicals, JSR) and process control leaders (like KLA, Applied Materials) is now inextricably linked to the multi-billion-dollar High-NA platform. These "enablers" are both a key source of risk and a significant investment opportunity.

The Dawn of the Angstrom Era—A Calculated Gamble

In conclusion, High-NA EUV is undoubtedly a technological marvel, born from a series of ingenious and complex engineering trade-offs , providing the clearest path for the semiconductor industry towards higher-resolution, single-exposure patterning. However, its economic viability is not a foregone conclusion but depends on a delicate balance between throughput, dose requirements, and the cost of multi-patterning alternatives.   

The road to mass production is a trial filled with ecosystem challenges. From the maturation of photoresists and the commercialization of durable CNT pellicles to the perfection of stitching technology and the full deployment of next-generation inspection tools, each element is an indispensable prerequisite for success.   

The adoption of High-NA EUV is not a simple "yes or no" question, but a complex strategic choice of "when and how." The divergent paths of Intel, TSMC, and Samsung are the different answers they have given to this question based on their unique market positions, with each choice being a well-considered gamble. The ultimate solutions to these technical and economic challenges will not only determine the pace of Moore's Law but will also define the competitive landscape of the global semiconductor industry for the next decade. The dawn of the angstrom era has arrived, but the race to conquer this new continent has just begun.