The Glass Age: How Glass Substrates Are Leading the Next Revolution in High-Performance Semiconductor Packaging

The Inevitable Shift: Why High-Performance Packaging Needs a New Foundation

The semiconductor industry is at a fundamental inflection point. For decades, the transistor scaling dictated by Moore's Law was the golden rule driving exponential growth in computing power. However, as physical limits approach, the economic benefits and technical feasibility of shrinking transistors on a single chip are rapidly diminishing. The development costs and manufacturing complexity have skyrocketed for process nodes from 14nm down to 3nm and beyond. This slowdown in the scaling race has forced the industry to find new avenues to continue performance improvements, and the answer no longer lies solely within the silicon wafer itself.   

The Imperative of Chiplets and the Rise of Heterogeneous Integration

To meet this challenge, a new paradigm known as "Heterogeneous Integration" has emerged, with the chiplet architecture at its core. Instead of manufacturing a massive, expensive, and low-yield monolithic System-on-Chip (SoC), its functions are broken down into smaller, specialized chiplets. These chiplets can be manufactured using the process node best suited for their function—for example, high-performance computing cores on the most advanced 3nm process, while I/O or memory controllers use more cost-effective mature processes. Subsequently, these individual chiplets are reintegrated at the package level to work together as a single, powerful system.   

This model offers significant advantages: higher yields, lower costs, greater design flexibility, and faster time-to-market. It has become the mainstream approach, especially in the fields of Artificial Intelligence (AI) and High-Performance Computing (HPC). AI accelerators and server processors need to integrate vast computational units, High-Bandwidth Memory (HBM) stacks, and high-speed I/O, making monolithic chip design impractical. The chiplet architecture allows designers to tightly package multiple GPU cores with HBM stacks, breaking the limits of a single reticle size to achieve unprecedented compute density and memory bandwidth.   

The Substrate: The New Center of Gravity

With the proliferation of chiplet architectures, the value center of the semiconductor industry is undergoing a profound structural shift. In the past, the vast majority of value and technological innovation was concentrated in the "front-end" processing of the silicon wafer. However, as the integration challenge moves from within the chip to the package level, the "substrate"—which carries and connects these chiplets—has evolved from a passive support component into a core hub that determines the performance, power consumption, and reliability of the entire system.   

This new focus places unprecedented and stringent demands on the substrate. It is no longer just about connecting a single chip to a printed circuit board (PCB); it must now act as a miniature system board, undertaking the following critical tasks:

1. Ultra-High-Density Interconnects: The substrate must provide extremely fine wiring to connect tens of thousands of micro-bumps at speeds of several terabits per second, ensuring high-speed data exchange between chiplets.   

   
   

2. Stable Power Delivery: It must supply hundreds or even thousands of amperes of current to massive AI chip clusters while minimizing voltage drop and noise to ensure stable computation.   

   
   

3. Efficient Thermal Management: It needs to rapidly dissipate hundreds of watts of waste heat from tightly packed chiplets to prevent performance degradation or system damage due to overheating.   

   
   

4. Signal Integrity: It must maintain the clarity and integrity of signals at ultra-high frequencies, avoiding signal attenuation and crosstalk, which is crucial for high-speed SerDes and memory interfaces.   

   
   

This role change signifies a fundamental architectural inversion in the semiconductor industry. For decades, value was almost entirely concentrated on the silicon chip. Now, significant value and performance differentiation are shifting from the silicon chip to the package substrate. This shift is redefining the competitive landscape, making the strategic importance of substrate technology nearly equivalent to that of the lithographic process node for the chip itself. In the past, investors and analysts primarily focused on the nanometer race between TSMC, Samsung, and Intel; in the future, they must pay equal attention to these giants' strategies in package substrate technology. The choice of substrate has evolved from a simple cost consideration to a critical decision that defines the upper limits of a system's architecture. The substrate's bottleneck will directly become the performance bottleneck of the entire system. Therefore, finding a new substrate material capable of meeting the demands of next-generation chiplets is not just a technological upgrade, but a materials revolution that will determine the direction of computing architecture for the next decade.

Confronting the Limits of Organic Substrates in the Chiplet Era

For the past several decades, organic substrates, represented by Ajinomoto Build-up Film (ABF), have been the cornerstone of high-performance processor packaging. With its excellent insulation, low dielectric constant, and relatively mature manufacturing process, ABF material has successfully supported multiple generations of CPUs and GPUs. However, with the advent of the chiplet era, the explosive growth in package size and complexity has exposed the inherent physical and electrical flaws of ABF organic substrates, which are increasingly becoming a key bottleneck limiting the continued expansion of system performance.   

The Warpage Dilemma: A Crisis of Scale and Physics

The most fundamental and intractable challenge facing ABF substrates is the issue of their mechanical structural stability, known as "warpage". This problem stems from an unavoidable physical reality: the vast difference in the Coefficient of Thermal Expansion (CTE) between materials. The CTE of organic materials like ABF is approximately 15−17 ppm/∘C, while that of silicon chips is only about 3 ppm/∘C. This is a difference of more than five times.   

In the single-chip era, when package sizes were smaller, this difference could be managed through methods like underfill. However, in the chiplet era, to accommodate more computing units and HBM stacks, the package size of AI accelerators has dramatically increased, reaching dimensions such as 72×72 mm or larger. Over such a large area, the slight CTE mismatch is significantly amplified. When the package undergoes thermal cycling, especially during the reflow process at temperatures as high as 250−350∘C, the organic substrate expands and contracts far more than the silicon chip above it, causing the entire package to bend or twist like a bimetallic strip.   

This warpage is not a trivial deformation; it is the culprit behind catastrophic yield losses. Severe warpage can lead to:

• Open Solder Joints: Ball Grid Array (BGA) solder balls at the edge of the substrate are stretched, causing a disconnection from the PCB.   

  
  

• Solder Ball Shorts: BGA solder balls at the corners of the package collapse under pressure, bridging with adjacent balls and causing a short circuit.   

  
  

• Delamination: Different material layers within the substrate or between the substrate and the chip peel apart due to excessive stress.   

  
  

These defects directly lead to soaring manufacturing costs and reduced product reliability. To mitigate the warpage problem, the industry has adopted a seemingly straightforward solution: increasing the rigidity of the substrate. This is typically achieved by increasing the thickness of the substrate's core layer and stacking more layers. However, this is a losing battle. While this "thicken and stack" strategy does suppress warpage to some extent, it introduces a series of new, more intractable problems, making the package thicker, heavier, and more expensive, while severely degrading the all-important electrical performance.   

The Electrical Bottleneck: Signal Integrity Decay at Terabit Speeds

The increased substrate thickness and layer count intended to mitigate warpage have directly led to a disaster in electrical performance. The signal transmission path within the substrate becomes longer, and organic materials like ABF are not ideal media for high-frequency signals. Their key electrical properties—the dielectric constant (Dk​) and dissipation factor (Df​)—are relatively high (for example, ABF has a Dk​≈3.3 and Df​≈0.0044).   

As interconnect speeds between chiplets move towards 224 Gbps and beyond, high Dk​ and Df​ values cause severe signal attenuation (i.e., insertion loss) and distortion. The signal loses too much energy during transmission, and its waveform becomes blurred, making it difficult for the receiving end to accurately interpret 0s and 1s, leading to data transmission errors. This electrical bottleneck forces designers to adopt more complex circuit designs and signal compensation techniques, further increasing the package's complexity and power consumption, creating a vicious cycle.   

The Wall of Scaling: Reaching the Physical Limits of Interconnect Density

In addition to mechanical and electrical problems, organic substrates also face an insurmountable wall in manufacturing precision. Modern chiplet interfaces require extremely fine line/space (L/S) and high-density microvias to achieve massive I/O connections.   

Although advanced processes like the Semi-Additive Process (SAP) have pushed the L/S of organic substrates below 10μm, achieving ultra-fine lines of L/S≤2μm with high yield and stability on large, inherently warped organic panels is a huge challenge. The thermal expansion and contraction of the substrate during processing cause pattern distortion and misalignment, severely impacting yield. This directly limits the I/O density between chiplets, becoming a bottleneck for system bandwidth.   

The predicament of organic substrates is, in essence, a systemic failure of co-optimization. The "solution" (thickening and adding layers) adopted to solve the mechanical problem (warpage) directly worsens the electrical problem (signal loss) and the cost problem (more layers). This indicates that the technology is heading towards diminishing returns. The industry is trapped in a negative feedback loop: the pursuit of larger package sizes to accommodate more chiplets leads to more severe warpage; the increased substrate thickness to solve warpage, in turn, stifles the required high-speed electrical performance and routing density. This is no longer a bottleneck that can be solved through incremental engineering improvements, but an architectural impasse that requires a disruptive innovation at the fundamental material level.

The Clear Winner: The Multifaceted Material Advantages of Glass Substrates

Facing the systemic predicament exposed by organic substrates in the chiplet era, the semiconductor industry urgently needs a new material platform. Glass Core Substrate (GCS) is emerging as the frontrunner in this materials revolution, thanks to its unparalleled combination of advantages. Glass is not merely a simple replacement for organic materials; its comprehensive superiority in mechanical, thermal, electrical, and optical properties provides a fundamental solution to the current packaging bottlenecks.

Absolute Dominance in Mechanical and Thermal Properties

The core advantage of glass substrates lies in their exceptional mechanical and thermal stability, which directly addresses the chronic warpage issue of organic substrates.

• Tunable Coefficient of Thermal Expansion (CTE): Unlike the fixed high CTE of organic substrates, the CTE of glass can be precisely engineered by adjusting its chemical composition, allowing it to range from 3 to 10 ppm/∘C. This means the CTE of a glass substrate can be tailored to be extremely close to that of a silicon chip (approx. 3 ppm/∘C). This near-perfect match fundamentally eliminates the immense stress generated by material expansion differences during thermal cycling, thereby greatly suppressing warpage. Studies have shown that on large panels, the warpage performance of glass substrates is about 3 times better than that of organic substrates.   

  
  

• Superior Dimensional Stability and Rigidity: Glass is a highly rigid material, and its dimensional stability far exceeds that of organic polymers, making it less susceptible to changes in temperature and humidity. This provides an extremely flat and stable platform for the subsequent fabrication of fine circuits, a prerequisite for achieving high-density interconnects.   

  
  

• Ultimate Flatness: Advanced manufacturing processes, such as the fusion forming developed by companies like Corning, can produce large-sized glass panels with outstanding flatness and extremely low Total Thickness Variation (TTV). This near-perfect surface quality is crucial for high-yield chip assembly and fine-pattern lithography.   

  
  

Unparalleled Electrical Performance

In high-speed signal transmission, glass, as an excellent insulator, has electrical properties far superior to organic dielectric materials.

• Low-Loss Characteristics Born for High-Speed Signals: Glass has a very low dielectric constant (Dk​≈2.5−3.0) and an extremely low dissipation factor (Df​). This means that when high-frequency signals are transmitted through glass, both energy loss and signal distortion are minimal. In academic research, transmission lines based on glass have achieved ultra-low loss of only 0.3 dB even at frequencies as high as 220 GHz.   

  
  

• Intel's Technology Roadmap: Intel has explicitly stated in its technology roadmap that glass substrates can support the next generation of ultra-high-speed signal transmission at 448 Gbps while maintaining excellent signal integrity. Intel claims that achieving the same level of performance on traditional organic substrates would require a shift to complex and expensive optical interconnect solutions. The emergence of glass substrates extends the life of electrical interconnects, postponing the need for a full transition to optics.   

  
  

Granting Freedom in Architectural Design

The superior physical and electrical properties of glass substrates translate into unprecedented design freedom for system architects, enabling them to build larger, denser, and more powerful chip systems.

• Unprecedented I/O Density: The dimensional stability of glass makes it possible to fabricate ultra-fine lines on it, easily breaking through the 2μm L/S barrier that is difficult for organic substrates to overcome.   

  
  

• Higher Via Density: Through-Glass Via (TGV) technology allows for extremely high-density vertical interconnects on glass substrates. Intel's data shows that compared to the mechanical drilling of organic substrates, the via density of glass substrates can be increased by up to 10 times (TGV pitch of 100μm vs. organic substrate via pitch of 325μm).   

  
  

• Larger Packages and More Chips: Combining these advantages, glass substrates make it possible to manufacture larger packages without worrying about a collapse in yield. Intel claims that for the same package area, a glass substrate can accommodate 50% more chips. This is a decisive advantage for AI accelerators that need to integrate an increasing number of computing and memory units.   

  
  

Welcoming the Future of Optical Interconnects

The transparency of glass gives it a unique potential—to become the ideal platform for integrating electronics and photonics.

• Seamless Integration of Optoelectronic Components: The transparent nature of glass makes it highly suitable for co-packaging Electronic Integrated Circuits (EICs) and Photonic Integrated Circuits (PICs). Low-loss optical waveguides can be directly integrated within the substrate, greatly simplifying the alignment process between optical fibers and chips, and achieving ultra-high bandwidth, ultra-low latency optical I/O between chips.   

  
  

The following table summarizes the quantitative comparison of key performance indicators for glass core substrates versus traditional organic substrates and silicon, which serves as a benchmark.

Table 1: Comparative Analysis of Substrate Material Properties

Property	Silicon (Benchmark)	Glass Core Substrate (GCS)	Organic (ABF) Substrate
Coefficient of Thermal Expansion (CTE) (ppm/∘C)	∼3	3−10 (Tunable)	∼15−17
Warpage	Very Low	Extremely Low (~3x better than organic)	High
Dielectric Constant (Dk​) (@ 1 GHz)	∼11.9 (Semiconductor)	∼2.5−3.0	∼3.3
Dissipation Factor (Df​) (@ 1 GHz)	High (Semiconductor)	Very Low	Low to Medium (∼0.0044)
Minimum Line/Space (L/S) (μm)	<1 (Lithography)	<2	∼8 (Mass Production), <2 (Challenging)
Thermal Conductivity (W/m−K)	∼150	∼0.8−1.4	∼0.2−0.5
Via Density (Relative)	High (TSV)	Very High (TGV, ∼10x better than organic)	Baseline (Mechanical Drill)

This comparison table clearly shows that glass substrates exhibit immense potential as the next-generation platform for high-performance packaging across all key dimensions. It not only solves the inherent defects of organic substrates but also opens up new possibilities in performance and architectural design.

Industry Adoption and Strategic Positioning: A Race to Commercialization

The disruptive potential demonstrated by glass substrates has triggered a fierce strategic race among global semiconductor giants. This competition is not just about technological leadership, but about securing dominance in the AI and HPC markets for the next decade. From chip design companies to foundries and substrate manufacturers, the entire industry chain is accelerating its deployment, trying to secure a favorable position in this impending materials revolution.

Intel's Big Bet: A Decade in the Making to Reclaim Packaging Supremacy

In this race, Intel is undoubtedly the loudest and most aggressive advocate. Intel views glass substrates as a core pillar of its "Systems Foundry" strategy, aiming to provide unparalleled packaging solutions for the AI era.   

Intel's determination is not a spur-of-the-moment decision but stems from over a decade of deep cultivation. The company has invested more than $1 billion in this field, establishing a dedicated R&D and pilot line at its Chandler, Arizona facility, and has accumulated over 600 related patents. Its technology roadmap is clear: to introduce glass substrates into commercial products before 2030, with the pilot line expected to be operational by 2025. This indicates that for Intel, glass substrates are no longer just a forward-looking research project, but a strategic commercial plan with a clear timeline and substantial financial backing.   

Intel's strategic intent is twofold. On one hand, by being the first to master glass substrate technology, it aims to build an insurmountable moat for its own CPU and AI accelerator products, thereby gaining a differentiated advantage in the competition with AMD and NVIDIA. On the other hand, Intel plans to offer glass substrate packaging technology to external customers through its Intel Foundry Services, and may even license its technology, thereby creating new revenue streams and challenging TSMC's dominance in the advanced packaging field.   

The Korean Front: A Pincer Movement by Samsung and SKC/Absolics

Facing Intel's aggressive push, the South Korean semiconductor industry has moved swiftly, forming a dual offensive composed of Samsung and SKC's subsidiary, Absolics.

• Samsung: As a leading global Integrated Device Manufacturer (IDM), Samsung is well aware of the importance of advanced packaging. The company has launched a glass substrate pilot line at its Sejong plant and has set a goal of achieving commercialization by 2028. To shorten the learning curve, Samsung has also strategically recruited senior engineers with extensive experience in glass substrates from Intel to accelerate its R&D process.   

  
  

• SKC/Absolics: A joint venture between SK Group's SKC and equipment giant Applied Materials, Absolics aims to become the world's first professional supplier to mass-produce glass substrates. Absolics has invested $600 million in an advanced factory in Georgia, USA, a project that has also received funding under the US CHIPS Act, and plans to start mass production in 2025. As a dedicated materials supplier, Absolics has the potential to gain a first-mover advantage in the early market.   

  
  

It is noteworthy that there are continuous reports in the market that Samsung is actively seeking cooperation with Intel, possibly in the form of technology licensing or establishing a joint venture. This reflects Samsung's pragmatic strategic thinking: rather than starting from scratch to catch up with Intel's decade-long R&D accumulation, it is better to accelerate its own technology adoption through cooperation, thereby more effectively competing with their common rival, TSMC.   

The Foundry Leader's Response: TSMC's Strategic Defense

Although Intel is more high-profile in its public announcements, as the reigning king of advanced packaging, TSMC will not stand idly by. The rise of glass substrates directly threatens the future of TSMC's dominant CoWoS (Chip-on-Wafer-on-Substrate) packaging platform. CoWoS currently relies mainly on silicon interposers, and glass substrates are a highly potential alternative.

To meet this challenge, TSMC is actively deploying its defense strategy. It is reported that TSMC is not only developing its own glass substrate solutions but may also integrate them into the next-generation evolution of CoWoS. For example, its proposed CoPoS (Chip on Panel on Subsystem) concept explicitly mentions using glass or sapphire to replace silicon interposers on large panels. In addition, TSMC is also joining forces with its long-term supply chain partners, such as the world's largest substrate manufacturer Unimicron, to form a glass substrate ecosystem alliance, indicating that TSMC's investment in this technology is serious and long-term.   

The Pull from the Demand Side: The Push from AMD, NVIDIA, and Cloud Giants

This technological transformation is not only driven by suppliers but is also subject to strong pull from market demand. As leaders in the AI accelerator market, the choices of AMD and NVIDIA are indicative for the entire ecosystem.

• AMD: It is reported that AMD is actively testing glass substrates with multiple suppliers, including Shinko, Unimicron, AT&S, and Samsung Electro-Mechanics, and there are rumors that it may launch products using glass substrates as early as 2025-2026.   

  
  

• NVIDIA: Similarly, NVIDIA is rumored to be working closely with TSMC to develop glass substrate solutions for its future GPU products.   

  
  

The clear demand from the AI chip duo provides the strongest development momentum for the entire supply chain, prompting all links from materials to equipment to accelerate technological maturity and capacity building.

This race around glass substrates is essentially a new round of "packaging wars" in the semiconductor industry, with the core being the strategic game between Intel and TSMC. For Intel, this is an "offensive war" aimed at surpassing TSMC's mature CoWoS ecosystem, trying to establish new competitive barriers through a technological generation gap. For TSMC, this is a "defensive war" that must be won to eliminate Intel's threat and consolidate its leadership in advanced packaging. This technological arms race between the giants will inevitably accelerate the maturity and popularization of glass substrate technology.

Meanwhile, Intel's decision to license its glass substrate technology rather than keeping it completely exclusive is a brilliant move. Intel realizes that it cannot quickly build a global supply chain ecosystem sufficient to compete with TSMC on its own. By licensing technology to potential allies like Samsung, Intel can accelerate the formation of an "anti-TSMC alliance," using a relatively open GCS ecosystem to compete with TSMC's relatively closed CoWoS ecosystem. This points investors in a clear direction: the opportunity lies not only in betting on Intel itself but also in investing in the numerous companies within the ecosystem that will align with Intel's standard.

Table 2: Competitive Landscape and GCS Commercialization Roadmap

Player	Strategic Goal/Positioning	Key Investment	Pilot/Mass Production Timeline	Key Known Partners
Intel	Attacker; Tech Leader & Licensor	> $1B (Arizona R&D Line)	2025 Pilot; Before 2030 Mass Production	Actively building ecosystem, potential collaboration with Samsung
Samsung	Fast Follower; Challenger to TSMC	Sejong City Pilot Line	2028 Target Mass Production	Exploring tech collaboration with Intel
SKC/Absolics	Specialized Supplier; Market Pioneer	$600M (Georgia Factory)	2025 Target Mass Production	Applied Materials (JV Partner)
TSMC	Defender; Maintain Packaging Leadership	In-house R&D; CoPoS Concept	Not specified, but in active development	Unimicron and other supply chain partners
AMD / NVIDIA	Demand Drivers; First Adopters	Product development & supplier validation	Rumored 2025-2026 product launch	AMD: Multiple suppliers; NVIDIA: TSMC
Other Substrate Makers	Technology Followers	R&D Investment	Generally in R&D phase	Ibiden, Unimicron, AT&S, etc.

The Ripple Effect: Redefining Advanced Packaging Architectures

The introduction of glass core substrates signifies far more than a simple material replacement for existing organic substrates. It is a platform-level innovation whose superior combination of properties is fundamentally rewriting the design rules of advanced packaging, giving rise to new system architectures, and redefining the balance between performance, cost, and size.

Beyond CoWoS: Glass Interposers as a Disruptive Alternative

TSMC's CoWoS technology is the current gold standard for 2.5D packaging, its core being the placement of logic chips and HBM memory side-by-side on a large silicon interposer. Glass substrates can serve as a direct replacement for silicon interposers and exhibit significant advantages in several aspects.   

• Superior Electrical Performance: Silicon itself is a semiconductor, and even high-resistivity silicon has unavoidable electrical losses at high frequencies. Glass, as an insulator, has far lower loss than silicon, providing a cleaner signal path for ultra-high-speed communication between chips.   

  
  

• Cost and Size Advantages: The manufacturing of silicon interposers relies on expensive fab processes, and their size is limited by the size of a single wafer. Glass, on the other hand, can be manufactured into large rectangular panels much larger than a wafer at a lower cost, using processes similar to those for flat-panel displays.   

  
  

• Process Simplification: When making Through-Silicon Vias (TSVs) on a silicon interposer, an insulating layer must first be deposited to prevent signal leakage. Glass, being an insulator itself, does not require this step when making TGVs, simplifying the process and reducing costs.   

  
  

These advantages make glass interposers a highly attractive option, with the potential to provide higher electrical performance while reducing the cost of large-area advanced packaging, directly challenging TSMC's silicon-based CoWoS-S technology.

Enabling True Panel-Level Packaging (PLP)

One of the most revolutionary potentials of glass substrates is their ability to take semiconductor packaging from "wafer-level" to true "panel-level." The ability to manufacture large-sized rectangular glass panels (such as 515×510 mm or larger) with high yield is key to this leap.   

Compared to packaging on round wafers, Panel-Level Packaging (PLP) significantly increases area utilization to over 95%, whereas round wafers waste a large amount of edge material. In mass production, higher area utilization directly translates to lower unit production costs.   

In the past, although organic substrates also used panel processes, their inherent warpage and dimensional instability limited the ability to achieve ultra-fine lines on large panels. The superior dimensional stability and flatness of glass substrates perfectly solve this problem, making high-precision lithography and assembly on large panels possible. This also allows the semiconductor industry to directly leverage and utilize the mature large-panel processing equipment and experience accumulated over decades by the flat-panel display industry, thereby accelerating technological maturity and cost reduction.   

The Ultimate Integration Platform for System-in-Package (SiP)

With its ability to accommodate more chips, support higher I/O density, integrate optical components, and its excellent high-frequency performance, the glass substrate is becoming the ideal foundation for the next generation of complex System-in-Package (SiP).   

Future SiPs will no longer be limited to integrating logic and memory. The high stability and high-temperature resistance of glass substrates make it possible to directly integrate RF front-end modules, sensors, and even advanced integrated voltage regulators (IVRs) and other power management solutions on or within a single substrate. Intel specifically mentioned in its technical documents that the higher temperature capability of glass substrates enables advanced integrated power delivery solutions. This will greatly shorten the power delivery path, reduce power loss, and bring higher energy efficiency to the entire system.   

The glass substrate is not an incremental improvement but a platform-level leap. It successfully combines the advantages of two traditional technology routes: on one hand, it has the high-density routing capability similar to silicon interposers (such as L/S of less than 2μm and high-density TGVs); on the other hand, it benefits from large-panel manufacturing, possessing the cost-effectiveness of scale similar to organic substrates.

This "best of both worlds" characteristic breaks the dilemma that system architects previously faced when designing high-performance systems: either choose small-area, high-cost silicon interposers (like CoWoS-S) for ultimate performance, or sacrifice performance for large-area, low-cost organic substrates. The emergence of glass substrates creates a new category, allowing designers to build larger, more complex systems without sacrificing performance, while also controlling costs. This is why it is considered a "revolution" rather than an "evolution"—it fundamentally changes the design rules and economic models of high-performance computing systems and is expected to give rise to new product forms that were previously impossible due to technical or cost constraints.

Building the Glass Supply Chain: Challenges and Opportunities

Although the theoretical advantages and strategic value of glass substrates are clear, moving them from the laboratory to mass production requires overcoming a series of severe manufacturing challenges and building a new, complex supply chain ecosystem from scratch. This process is fraught with technical difficulties, but it also brings enormous innovation and investment opportunities for various segments of the industry chain.

The Core Challenge: Conquering Through-Glass Via (TGV) Manufacturing

Through-Glass Vias (TGVs) are the key technology for achieving vertical electrical interconnects in glass substrates. The yield, cost, and reliability of their manufacturing process are the biggest bottlenecks determining whether glass substrates can be successfully commercialized. The TGV manufacturing process mainly consists of two core steps: via formation and metal filling, each of which is challenging.

Via Formation

• Technical Routes: Current mainstream TGV formation technologies include laser drilling and etching. Laser drilling can use CO2 lasers or ultrashort pulse lasers (such as femtosecond lasers); etching methods include wet etching, plasma etching, and an advanced technology that combines laser and etching—Selective Laser-induced Etching (SLE).   

  
  

• Manufacturing Challenges:

  1. Throughput and Speed: High-performance packaging requires tens of thousands or even hundreds of thousands of TGVs. How to process at a high throughput of thousands of holes per second is key to controlling costs.   

     
     

  2. Quality Consistency: The shape of each via, including taper angle and roundness, must be precisely controlled. Any inconsistency will affect the quality of the subsequent metal filling.   

     
     

  3. Microcracks and Debris: The brittleness of glass makes it highly susceptible to microcracks and chipping during processing. These tiny structural defects can severely weaken the mechanical strength of the substrate and become a hidden danger for future reliability failures.   

     
     

  4. Residue Management: Debris and residue generated during laser ablation or etching, if not effectively removed, can clog the vias and hinder the subsequent metallization process.   

     
     

Metallization and Filling

• Process: After via formation, a conductive seed layer needs to be deposited on the via walls, and then copper is completely filled into the vias through processes like electroplating to form a conductive path.   

  
  

• Manufacturing Challenges:

  1. Void-Free Filling: Achieving completely void-free copper filling in tiny, high-aspect-ratio vias is extremely challenging. Any tiny void will lead to increased resistance or even an open circuit, directly causing electrical failure.   

     
     

  2. Adhesion: The adhesion between copper and the smooth glass via walls is another key issue. If the adhesion is insufficient, the copper pillars and glass may delaminate under subsequent thermal stress, destroying the electrical connection.   

     
     

  3. Copper Diffusion: Copper atoms may gradually diffuse into the surrounding glass medium over time and with temperature changes, which could lead to a decrease in insulation performance and cause long-term reliability problems.   

     
     

Reliability Verification

The long-term reliability of the TGV structure is key to its market acceptance. There is a significant CTE mismatch between the copper filled in the vias (CTE approx. 17 ppm/∘C) and the surrounding glass (CTE approx. 3−10 ppm/∘C). In repeated thermal cycling, this difference generates continuous stress, which may lead to copper pillar protrusion, glass cracking, or interface delamination. Intel has also acknowledged that stress management is one of the key issues they are actively addressing. Therefore, the long-term stability of the TGV structure must be verified through rigorous accelerated aging tests.   

The manufacturing of TGVs, especially the control of their yield, cost, and reliability, is undoubtedly the most critical chokepoint on the path to the commercialization of glass substrate technology. It is not only the most technically complex part but also the lifeline that determines the economic viability of the entire technology route. Therefore, any company that can achieve a breakthrough in high-throughput, defect-free TGV processing technology—whether it's an equipment supplier developing a new laser source or a materials supplier inventing new etching chemicals—will hold the key to unlocking the entire glass substrate market. This makes the TGV process ecosystem the most active area for venture capital and a core area for investors to watch closely.

Table 3: TGV Manufacturing Challenges and Emerging Solutions

Process Step	Key Challenge	Main Technology/Solution	Key Players/Innovators
Via Drilling (Formation)	Throughput, microcracks, shape control, debris	Ultrashort pulse laser (fs/ps) drilling, Selective Laser-induced Etching (SLE), plasma etching	Equipment vendors (Philoptics, DR Laser), research institutes
Via Wall Quality	Surface roughness, taper	Optimized laser parameters, chemical polishing, double-sided drilling	Equipment vendors, process developers
Metallization/Filling	Void-free filling, adhesion, copper diffusion	Advanced electroplating chemicals, PVD/CVD seed layers, barrier layer materials	Material suppliers, process developers
Mechanical Reliability	Stress from Cu-glass CTE mismatch	Optimized glass CTE, annealing for stress relief, structural design (e.g., hourglass vias)	Glass suppliers (Corning), substrate manufacturers (Intel)

Mapping the Emerging Ecosystem

The rise of the glass substrate industry requires a new supply chain, from raw materials to end applications. This emerging ecosystem is creating new market opportunities for various types of companies.

• Specialty Glass Innovators: The source of the supply chain is the development of specialty glass. Materials science giants like Corning and AGC are playing a key role. They are developing specialized glass formulations with specific CTEs, high purity, high strength, and the ability to be made into large, ultra-flat panels.   

  
  

• Process and Equipment Suppliers: This is one of the areas with the most concentrated opportunities. The market needs a whole new set of production equipment:
  

  • Laser Processing Equipment: Companies developing high-throughput, high-precision laser systems for TGV formation, such as Philoptics, DR Laser, and Workshop of Photonics.   

    
    

  • Panel Handling and Lithography Equipment: Automated handling, cleaning, and fine-line exposure equipment suitable for processing large, fragile glass panels, which needs to be introduced or adapted from the flat-panel display and PCB industries.   

    
    

  • Metrology and Inspection Equipment: Advanced optical and X-ray inspection systems capable of high-speed detection of TGV microcracks, filling defects, and alignment accuracy.   

    
    

• Substrate Manufacturers: This field includes two types of players. One type is the traditional organic substrate giants, such as Ibiden, Unimicron, and AT&S, who are actively investing in R&D to avoid being left behind in the new technology wave. The other type is emerging specialized manufacturers focusing on glass substrates, such as Absolics, who are expected to seize a first-mover advantage with their focus and flexibility.
  

• Foundries and OSATs: Leaders like TSMC, Intel, and Samsung, as well as traditional Outsourced Semiconductor Assembly and Test (OSAT) companies, must develop and validate new assembly and testing processes to handle large, rigid glass substrate packages and ensure their final reliability.   

  
  

Strategic Outlook: Navigating the Transition in an AI-Driven Future

The rise of glass core substrates marks a profound paradigm shift in the field of semiconductor packaging. For industry players and investors, understanding the timeline of this transition, identifying key opportunities in the value chain, and discerning its long-term impact are fundamental to formulating future strategies.

Adoption Timeline: From Niche Markets to Mainstream Applications

The commercialization of glass substrates will follow a path of gradual diffusion from high-end niche markets to broader applications.

• Initial Adoption (2026-2028): The first commercial applications of glass substrates will be concentrated in areas with extremely high performance requirements and relatively low cost sensitivity. This primarily includes top-tier AI accelerators and HPC processors for data centers and supercomputers. Flagship products from companies like Intel, AMD, and NVIDIA will be the first adopters. This timeline aligns with the technology roadmaps and mass production plans announced by major players.   

  
  

• Diffusion Phase (Post-2030): As TGV manufacturing technology matures, yields improve, and costs decrease due to mass production, the application scope of glass substrates will expand. Thanks to its excellent high-frequency, low-loss characteristics, it will become the ideal choice for next-generation (6G) communication RF modules. In addition, the advanced automotive electronics sector, with its stringent requirements for reliability and high performance, will also become a significant potential market. The global market for glass in semiconductors is expected to see significant growth, with its market size potentially reaching several billion dollars by the mid-2030s.   

  
  

The Investment Thesis: Identifying Winners in the Value Chain

In this technological transition, companies in different segments will realize their value at different time windows.

• Short-Term (1-3 years): Investment opportunities will be mainly concentrated on the "pick-and-shovel" plays. The most direct and earliest beneficiaries will be the companies that provide the core tools and raw materials for glass substrate production. This includes specialized equipment manufacturers developing new laser drilling, precision metrology, and automated handling systems, as well as raw material suppliers like Corning and AGC that can stably supply high-quality, large-sized specialty glass panels.
  

• Mid-Term (3-5 years): As the technology gradually matures, the focus of competition will shift to substrate manufacturing itself. Substrate manufacturers (such as Absolics, Intel, Samsung, etc.) that are the first to achieve high-yield, large-scale mass production will be able to dominate the lucrative high-end HPC/AI market and enjoy significant pricing power and market share.
  

• Long-Term (5+ years): The ultimate victory will belong to the chip design companies (like Intel, AMD, NVIDIA) that can most effectively utilize the architectural freedom granted by glass substrates to create products with a generational advantage. At the same time, the foundries or OSATs that successfully build the most efficient, scalable, and cost-effective glass substrate packaging ecosystem will also lock in their long-term leadership position in this protracted battle.

A Foundational Enabler, Not an Incremental Upgrade

It must be clear that the transition from organic to glass substrates is by no means a simple material replacement. It is a fundamental, ground-up platform revolution. It removes the physical and electrical shackles long imposed on system architecture by organic materials, opening up a new path for performance growth beyond Moore's Law.

Glass substrates directly enable the continued scaling of chiplet systems, and it is these increasingly large and complex chiplet systems that will drive the development of artificial intelligence and high-performance computing for the next decade. Although the manufacturing challenges ahead are still formidable and initial costs will be high, the fundamental advantages of glass in physical and electrical properties make its adoption in high-performance applications a matter of "when," not "if."

For all stakeholders and investors in the semiconductor industry, a deep understanding and accurate grasp of the context, pace, and opportunities of this transition will be key to identifying the next wave of industry leaders and securing a winning position in the coming "Glass Age."