What’s the Difference Between CoWoS-S, CoWoS-R, and CoWoS-L? The Three-Act Evolution of TSMC's Packaging

From silicon interposers to packaging behemoths, each CoWoS variant has its own battlefield.

In the world of semiconductors, some innovations quietly reshape the future. When TSMC introduced a packaging technology called CoWoS in 2012, few anticipated how central it would become to the AI hardware revolution.

Now, at the crossroads of exploding AI model sizes and escalating hardware demand, one realization stands out: how chips communicate with each other is just as important as how they compute—and that’s the realm of packaging.

Some say Moore’s Law has hit a wall, and engineers have turned to stacking silicon like Lego blocks. But CoWoS isn’t about stacking—it’s about integration: ultra-high bandwidth, low latency, and system-level efficiency.

In this article, we put the entire CoWoS family under the technical microscope. You’ll discover how each variant—S, R, and L—is designed to meet distinct performance, cost, and integration needs.

What is CoWoS and Why Does It Matter?

CoWoS (Chip-on-Wafer-on-Substrate) is TSMC’s flagship 2.5D advanced packaging technology, introduced in 2012 to tackle the post-Moore’s Law performance ceiling. It integrates multiple chiplets onto a silicon interposer, which is then connected to a package substrate. This heterogeneous integration allows logic dies (e.g. processors) and HBM (High Bandwidth Memory) to coexist with ultra-short interconnects, delivering massive bandwidth and lower power.

CoWoS is a milestone in packaging evolution, shifting from traditional 2D chip designs to spatial integration across chiplets. Instead of routing signals across long PCB traces, CoWoS enables near-die communication that’s fast, power-efficient, and scalable—perfect for AI model training, large memory bandwidth applications, and high-performance computing (HPC).

The Three CoWoS Variants: S, R, and L

🔹 CoWoS-S (Silicon Interposer)

✅ Officially confirmed by TSMC: CoWoS-S uses a silicon interposer with TSV (Through-Silicon Vias), supports HBM integration, and is used in chips like NVIDIA H100. Max interposer size: ~2500 mm².

CoWoS-S is the most mature and widely adopted variant. It uses a monolithic silicon interposer with TSVs to connect logic dies and memory. The interposer acts like a mini-motherboard, offering high-density wiring, short distances, and excellent signal integrity.

In practice, CoWoS-S powers chips like NVIDIA’s H100 and AMD’s MI300. These devices feature multiple chiplets and stacks of HBM interconnected via thousands of ultra-fine wires. However, silicon interposers are costly and constrained in size due to photolithography limits—currently around 2500 mm².

🔹 CoWoS-R (Redistribution Layer Based)

✅ CoWoS-R utilizes RDL (Redistribution Layers) and localized silicon interposers to lower cost and increase design flexibility for AI ASICs and mid-range accelerators.

CoWoS-R is designed for applications where bandwidth is needed, but cost sensitivity is critical. Rather than using a full silicon interposer, CoWoS-R introduces RDL technology—multi-layer wiring built on top of the package substrate—to redistribute I/O and reduce interposer size.

RDL lacks the ultra-fine pitch and signal performance of silicon, but it offers significant savings and design flexibility. It’s ideal for domain-specific AI chips (e.g., IPUs), mid-tier accelerators, or networking chips where extreme bandwidth isn’t required.

🔹 CoWoS-L (Large Interposer)

✅ CoWoS-L extends CoWoS-S by combining it with LSI (Local Silicon Interconnect) technology and silicon bridge stitching to break the 2500 mm² limit. Aimed at large-scale AI systems like NVIDIA Blackwell (GB200).

CoWoS-L is TSMC’s answer to massive model-scale compute. It goes beyond CoWoS-S by enabling extra-large silicon interposer areas—over 3000 mm²—by stitching multiple interposer segments using LSI technology.

This allows for more chiplets and HBM stacks in a single package, enabling next-generation AI training systems that need terabytes of bandwidth and dense compute. However, larger size also introduces thermal, mechanical, and yield challenges, which limit its adoption to flagship products.

CoWoS Comparison Table

To help you quickly understand the trade-offs between the three CoWoS variants, here’s a feature comparison table outlining key technical, performance, and cost factors:

Variant	Interposer Design	Core Feature	Bandwidth	Cost	Application Scope	Example Products
CoWoS-S	Silicon Interposer + TSV	High bandwidth, mature tech	High	High	AI accelerators, HPC	NVIDIA H100, AMD MI300
CoWoS-R	RDL + Local Interposer	Cost-efficient, flexible	Medium	Moderate	AI ASICs, IPUs	Custom AI accelerators
CoWoS-L	Large stitched interposer	Extreme area & integration	Ultra-High	Very High	AI training, GPU compute	NVIDIA GB200 (rumored)

Why CoWoS Is TSMC’s Hidden Weapon

As monolithic chip scaling becomes harder, advanced packaging is taking center stage. CoWoS sits at the heart of this transformation—enabling chiplet integration, HBM stacking, and ultra-dense I/O—all while aligning seamlessly with TSMC’s cutting-edge N5/N3 process nodes.

Whether you’re building a datacenter GPU, a specialized AI ASIC, or a next-gen server processor, CoWoS offers the infrastructure to do more with less silicon. As AI models demand more memory, interconnect, and compute, CoWoS will play an even more strategic role.

Packaging is no longer the last step—it’s the battleground.

Takeaway

CoWoS-S, R, and L represent not just different packaging technologies, but different philosophies of performance trade-offs. CoWoS-S optimizes bandwidth and signal integrity, CoWoS-R balances cost and configurability, and CoWoS-L goes big—literally—to meet future AI compute demands.

These aren’t just technical choices—they’re strategic decisions made by chipmakers to shape the future of AI infrastructure.

So next time you hear about an AI breakthrough, remember: it’s not just about smarter algorithms—it’s also about smarter packaging.