GAAFET Unveiled: A Deep Dive into the Metrology, Materials, and Yield Challenges of the 2nm Node – The Key to the Angstrom Era

Imagine if your smartphone responded ten times faster, if power consumption for complex computations was drastically reduced, or if even more powerful artificial intelligence applications could be driven – the realization of all these visions depends heavily on the continuous evolution of a tiny component, tens of thousands of times smaller than the diameter of a human hair: the transistor. For decades, the semiconductor industry, as if chasing the Holy Grail of Moore's Law, has relentlessly made transistors smaller, faster, and more power-efficient. However, as mainstream FinFET (Fin Field-Effect Transistor) technology approaches its physical limits below 3nm, its scaling benefits are gradually diminishing, and issues like short-channel effects and leakage current are becoming increasingly severe. At this critical juncture, GAAFET (Gate-All-Around Field-Effect Transistor) technology shoulders the responsibility of building on past achievements and paving the way for the future, regarded as the key to extending semiconductor brilliance and tackling the 2nm node and even more advanced process nodes.

This article will take you deep into the microscopic world of GAAFETs. We will not only analyze their operating principles and structural advantages but also focus on the three core challenges – "Metrology," "Materials," and "Yield" – that must be confronted head-on as they advance towards the cutting-edge 2nm process node. Together, we will also envision how this transformative technology will lay a solid foundation for our digital future.

What is GAAFET? Why is it Crucial in the 2nm Era?

Before discussing GAAFETs, let's briefly review the history of transistor scaling. Each advancement in process nodes means more transistors can be integrated onto a chip of the same area, bringing greater computing performance and lower unit costs. This is the fundamental driving force behind the ever-evolving world of tech products.

The Long Road of Semiconductor Process Scaling and Physical Limits

From early Planar FETs to later FinFETs, engineers have continuously sought more effective ways to control the current channel to suppress the leakage current and short-channel effects that intensify with shrinking dimensions. However, as processes entered the 5nm and 3nm nodes, the fin structure of FinFETs faced bottlenecks in further scaling. Its gate could only control the channel from three sides, and its electrostatic control capabilities had reached their limits.

GAAFET: The Successor to FinFET, Carrying the Hope for Moore's Law

The emergence of GAAFET has brought new dawn to the semiconductor industry. Its core concept is to have the gate material completely envelop the entire current channel. Whether the channel is in the form of nanowires or wider nanosheets, near-perfect four-sided or all-around electrostatic control can be achieved. This structural leap gives it potential superior to FinFETs in suppressing leakage current, enhancing drive current, and reducing operating voltage, making it the ideal choice for the 2nm and future Ångström era. Samsung was the first to introduce its nanosheet GAAFET technology, called MBCFET (Multi-Bridge Channel FET), at the 3nm node, while TSMC and Intel also plan to introduce GAAFET architecture at the 2nm node, demonstrating its strategic importance.

In-depth Analysis of GAAFET Core Principles

GAAFET is not a technology achieved overnight; its birth is the inevitable result of the evolution of transistor structures, aimed at solving the physical limitations faced by previous-generation technologies.

The Evolutionary Path from Planar FET to FinFET, and then to GAAFET

Limitations of Planar FET

In traditional Planar FETs, the gate is located only above the channel. As the gate length continuously shrank, the electric fields from the source and drain had an increasing influence on the channel. This weakened the gate's control over the current, leading to severe short-channel effects and leakage current issues, much like a leaky faucet.

The Rise and Contribution of FinFET

To solve this problem, FinFETs were designed with a three-dimensional fin-like channel, allowing the gate to surround the channel on three sides. This significantly improved electrostatic control and successfully advanced semiconductor processes to the 7nm and even 5nm generations, playing a pivotal role for over a decade.

Structural Advantages of GAAFET: Nanosheets and Nanowires

GAAFET takes this a step further by fabricating the channel as nanowires or a stack of multiple nanosheets, completely enveloped by the gate material. Nanowire GAAFETs have channel cross-sections of circular or square thin wires. Nanosheet GAAFETs, on the other hand, design the channel into flat, sheet-like structures. By stacking multiple nanosheets, a larger effective channel width can be achieved within the same footprint, thereby increasing the drive current. Currently, mainstream manufacturers are leaning towards nanosheet structures for the 2nm node due to their advantages in performance and process integration.

Basic Structure and Operating Principle of GAAFET

Superior Electrostatic Control

Because the gate material completely wraps around the channel, GAAFETs can maximize the gate's control over carriers (electrons or holes) within the channel. This means transistors can be effectively turned on or off at lower voltages, and current can be more effectively prevented from "leaking" when the transistor is in the off state.

Effective Reduction of Leakage Current and Short-Channel Effects

The direct benefit of excellent electrostatic control is a significant reduction in leakage current and a notable suppression of various short-channel effects, such as Drain-Induced Barrier Lowering (DIBL). This allows GAAFETs to maintain good switching characteristics even at extremely small dimensions, providing the possibility for continued scaling.

Key Challenge 1: Precision Metrology for 2nm GAAFETs

When the characteristic dimensions of transistors shrink to the atomic scale of 2nm, any minute process deviation can lead to huge differences in device performance or even failure. This poses unprecedented challenges for metrology technology.

"A Hair's Breadth Difference Leads to a Thousand Miles' Error" at the Nanoscale

At the 2nm node, the thickness of GAAFET nanosheets may be only a few nanometers, and the spacing between sheets is also extremely small. Precise measurement and control of these dimensions are fundamental to ensuring consistent transistor performance; any atomic-level fluctuation can affect the final chip's operation.

Measurement Complexity Introduced by 3D Structures

Compared to FinFETs, the multi-layered stacked nanosheet structure of GAAFETs is more complex. Many critical dimensions are hidden within the structure, making them difficult for traditional surface metrology techniques to access.

Precise Control of Nanosheet Thickness, Width, and Spacing

Accurately measuring the thickness, width, and shape of each nanosheet, as well as their vertical spacing and alignment accuracy, is a huge challenge. These parameters directly affect the transistor's current magnitude and switching speed.

Non-destructive Inspection of Buried Interfaces and Defects

The quality of the interface between nanosheets and the gate dielectric, as well as the source/drain regions, is crucial. Any interface defects or contaminants can become leakage paths or performance killers. Developing innovative metrology methods to inspect these buried, minute defects without destroying the device structure is necessary.

Demand and Development of Advanced Metrology Techniques

To address these challenges, the industry is actively developing and implementing more advanced metrology techniques, such as:

• Optical Critical Dimension (OCD) Metrology: By analyzing the scattered light spectrum resulting from the interaction of light with nanostructures, critical dimensions of the structure can be reverse-engineered. This method offers non-destructiveness and high throughput.
  

• X-ray Metrology Techniques: Techniques like Critical Dimension Small-Angle X-ray Scattering (CD-SAXS), X-ray Reflectivity (XRR), and X-ray Fluorescence (XRF) utilize the penetrating power of X-rays to obtain information about deeper structures and material compositions.
  

• Enhancements in Electron Microscopy: While Transmission Electron Microscopy (TEM) and Scanning Electron Microscopy (SEM) are mainly used for analysis during process development, their resolution and automation levels are continuously improving to provide finer structural verification.

Key Challenge 2: The Materials Science Revolution for 2nm GAAFETs

In addition to structural innovation, the realization of GAAFETs also heavily relies on breakthroughs in materials science. From the channel and gate dielectric to the metal gate, new materials and precision processes are required.

Innovation in Channel Materials: Silicon's Limits and the Search for Alternatives

Although silicon (Si) remains the mainstream channel material, its carrier mobility is difficult to improve at extremely small scales.

• Strained Silicon-Germanium (SiGe): Introducing strained SiGe as the channel material in P-type transistors (PMOS) can improve hole mobility. This has become standard practice in the FinFET era and will continue into GAAFETs. For NMOS, strained silicon or other high-mobility materials might be explored.
  

• Other III-V or 2D Materials: Although not yet widely used, academia and industry continue to research the potential of III-V compound semiconductors like Indium Gallium Arsenide (InGaAs), or 2D materials like Molybdenum Disulfide (MoS₂), as future channel materials due to their higher electron mobility.

New Requirements for High-k Gate Dielectrics

To maintain sufficient gate capacitance for effective channel control while shrinking dimensions, high-k (high dielectric constant) materials are needed to replace traditional silicon dioxide.

Balancing Interface Quality and Leakage Current

In GAAFETs, the high-k material needs to perfectly conform to the nanosheet channel, ensuring a high-quality interface with the channel to reduce interface trap density (Dit) and suppress leakage current. Commonly used materials like Hafnium Dioxide (HfO₂) and its improved versions remain key research focuses.

Continuous Scaling of Equivalent Oxide Thickness (EOT)

The industry pursues lower EOT to improve performance, but excessively thin dielectrics can easily lead to leakage and reliability problems. Achieving a balance between these two is a major challenge.

Optimization of Metal Gates and Contact Resistance

In conjunction with high-k dielectrics, metal gate materials with specific work functions are needed to precisely control the transistor's threshold voltage (Vt). Furthermore, as device dimensions shrink, the contact resistance between the source/drain and the channel accounts for an increasingly large proportion of the total resistance, becoming a major bottleneck limiting performance. New low-resistance contact materials and technologies need to be developed.

Precision Processes like Atomic Layer Deposition (ALD) and Atomic Layer Etching (ALE)

GAAFET manufacturing relies heavily on process technologies capable of atomic-level precision control. Atomic Layer Deposition (ALD) can deposit thin films with uniform thickness and excellent conformality, crucial for making high-k dielectrics and metal gates. Atomic Layer Etching (ALE) can remove materials with atomic-level precision, vital for nanosheet release and patterning. The stability and efficiency of these technologies directly impact GAAFET performance and yield.

Key Challenge 3: The Yield Enhancement Dilemma for 2nm GAAFETs

Even with precision metrology tools and advanced materials, integrating billions, or even tens of billions, of fully functional and consistent GAAFET transistors onto a single wafer and achieving acceptable yield remains one of the most formidable challenges of the 2nm generation.

Risk of Accumulated Errors from Increased Process Steps

The manufacturing flow for GAAFETs is more complex than for FinFETs. For example, it requires growing multiple layers of different thin films (e.g., alternating Si/SiGe stacks) via epitaxy, followed by selective etching of sacrificial layers to form suspended nanosheet channels. Each additional process step can introduce new sources of variation or defects, increasing the risk of accumulated errors.

Consistency Challenges in Nanosheet Stacking and Patterning

Ensuring high consistency in the thickness, width, morphology of each nanosheet, and their vertical alignment is extremely challenging. During nanosheet release, preventing structural collapse, distortion, or breakage also tests the limits of process control.

The Role and Challenges of EUV Lithography

Extreme Ultraviolet (EUV) lithography is core to achieving 2nm patterning. However, it faces issues like stochastic effects leading to Line Edge Roughness (LER), Line Width Roughness (LWR), and pattern defects. In GAAFETs, these minute pattern deviations can significantly impact the final device's electrical properties.

Defect Density Control and Defect Source Analysis

As device dimensions shrink, previously tolerable minor defects can become fatal flaws at the 2nm scale. Effectively reducing overall defect density and quickly and accurately locating and analyzing the sources of new types of defects (e.g., interlayer defects generated during nanosheet stacking, residues from ALD/ALE processes) are key to improving yield.

Integration Complexity and Cost Considerations

The high complexity of the GAAFET process is not only a major technical test but also directly drives up R&D and manufacturing costs. How to balance the pursuit of ultimate performance with production efficiency and cost-effectiveness is a realistic issue that semiconductor manufacturers must face.

Summary of Key Challenges: GAAFET's Three Major Battles (Table Format)

Challenge Area	Specific Issues	Potential Solutions/Research Directions
Precision Metrology	Difficult to precisely control nanosheet dimensions (thickness, width, spacing)	Develop high-resolution OCD, advanced X-ray metrology (CD-SAXS, XRR), enhance electron microscopy analytical capabilities.
	Difficult to inspect buried interfaces and minute defects in 3D structures	Develop non-destructive inspection techniques, combine multiple metrology methods for comprehensive analysis, introduce AI-assisted defect identification.
Materials Science	Carrier mobility bottleneck in silicon-based channel materials	Introduce strain engineering (e.g., SiGe), explore III-V compound semiconductors or 2D materials as new channels.
	Leakage and reliability of ultra-thin High-k dielectrics	Develop new High-k materials, optimize High-k/channel interface quality, improve properties through material stacking or doping.
	Rapid increase in contact resistance with shrinking dimensions	Research new low-resistance contact materials, optimize contact interface processes, adopt new contact structure designs.
Yield Enhancement	Increased risk of accumulated errors and defects due to numerous process steps	Strictly control uniformity and stability of each process step, strengthen in-situ metrology.
	Difficulty ensuring consistency and structural integrity of nanosheet stacking, release, and patterning	Optimize epitaxial growth and selective etching processes, improve pattern fidelity and coverage of EUV lithography, develop stress control techniques to prevent structural collapse.
	Emergence and identification of new types of defects difficult	Establish defect libraries and analysis methodologies for GAAFETs, use big data and machine learning for defect prediction and classification.

GAAFET Technology Comparison and SWOT Analysis

To better understand GAAFET's positioning, we can compare it with the preceding FinFET technology.

GAAFET vs. FinFET: A Comprehensive Comparison

Feature Dimension	FinFET	GAAFET (Nanosheet)
Structural Feature	Fin-shaped channel, gate on three sides	Nanosheet channel, gate on four sides/all-around
Gate Control	Good	Excellent
Leakage Current	Relatively higher	Lower
Short-Channel Effect Suppression	Better	Very good
Drive Current	Can be increased by adding more fins	Can be flexibly increased by adjusting nanosheet width and stack count
Design Flexibility	Fin height fixed, width adjustment limited	Nanosheet width adjustable, greater design freedom (Vt tuning)
Process Complexity	Relatively mature, but scaling faces challenges	Higher, especially in nanosheet formation and stacking
Main Application Nodes	22nm to 3nm (some manufacturers)	3nm (some manufacturers) and 2nm onwards

Characteristic Differences Between Nanosheet vs. Nanowire GAAFET Structures

Generally, nanowire GAAFETs offer the best electrostatic control but have a smaller effective channel width, leading to relatively limited drive current. Nanosheet GAAFETs, by widening the channel (forming a sheet) and stacking them, can significantly increase drive current while maintaining good electrostatic control. This makes them the mainstream choice for the current 2nm node. The width of the nanosheets can also be used as a design parameter to adjust the threshold voltage, increasing design flexibility.

GAAFET Application Scenarios and Market Potential

The successful introduction of GAAFET technology will bring revolutionary changes to many fields with extremely high demands on performance and power consumption.

High-Performance Computing (HPC) and Data Centers

HPC and data centers need to process massive amounts of data and complex computing tasks, with an insatiable demand for chip computing power and energy efficiency. GAAFETs bring higher performance and lower power consumption, helping to build more powerful supercomputers and more energy-efficient data center infrastructures.

Artificial Intelligence (AI) and Machine Learning Chips

AI model training and inference demand huge computing resources. The higher transistor density and better PPA (Performance, Power, Area) offered by GAAFETs will enable AI chips to integrate more computing units in a smaller area, accelerating the development and popularization of AI technology, benefiting applications from the cloud to edge devices.

Mobile Devices and Low-Power Applications

For battery-powered mobile products like smartphones and wearable devices, power consumption is a critical consideration. GAAFETs can operate at lower voltages, effectively reducing power consumption, extending battery life, and simultaneously enhancing the ability to handle complex applications.

Other Forward-Looking Application Areas

In addition to the main areas mentioned above, GAAFET's potential will also extend to emerging applications such as autonomous driving, the Internet of Things (IoT), and the metaverse. These fields also have high expectations for chip performance, power consumption, and integration levels.

Future Development Trends and Technological Outlook

Although GAAFET is currently the most advanced transistor architecture, the exploration of semiconductor technology never ends, and GAAFET itself has room for continuous evolution.

The Possibility of Stacked GAAFETs (CFETs)

Complementary FETs (CFETs) are considered one of the potential successor technologies to GAAFETs. The concept of CFET is to stack NMOS and PMOS transistors vertically instead of placing them side-by-side, thereby significantly reducing the area of standard logic cells and achieving higher transistor density. This requires overcoming more complex process integration challenges on top of the GAAFET foundation.

Introduction of 2D Materials

As mentioned earlier, 2D materials represented by Transition Metal Dichalcogenides (TMDCs) such as Molybdenum Disulfide (MoS₂) and Tungsten Diselenide (WSe₂), are considered promising candidates to replace silicon as channel materials in the future due to their atomic-level thickness, excellent carrier mobility, and dangling-bond-free surfaces. They hold the promise of more extreme scaling and lower power consumption.

System-Technology Co-Optimization (STCO) and Design-Technology Co-Optimization (DTCO)

As process technology becomes increasingly complex, relying solely on transistor scaling is no longer sustainable. In the future, there will be a greater emphasis on System-Technology Co-Optimization (STCO), which involves considering and co-optimizing chip design, process technology, packaging technology, and other aspects holistically. For example, advanced packaging technologies (like chiplet designs) can be used to integrate chips from different process nodes or functionalities to maximize overall system performance. Design-Technology Co-Optimization (DTCO) focuses more on fully considering process limitations and characteristics during the design phase to achieve the best PPA.

The Advent of the Ångström Era

With the maturation of GAAFET technology and the exploration of future structures like CFETs, the semiconductor industry is moving towards the Ångström era (1 Å = 0.1 nm). This not only represents an extreme challenge in manufacturing processes but also heralds another giant leap in computing power.

Conclusion: GAAFET – Overcoming Challenges to Lead Semiconductors into a New Era

The emergence of GAAFET technology is an important milestone on the semiconductor industry's path towards extreme scaling. It not only successfully succeeds FinFET, providing a viable path for the realization of 2nm and more advanced process nodes, but also opens up new imaginative possibilities for future chip performance improvements with its excellent electrostatic control and design flexibility.

However, the road to success is never smooth. As analyzed in depth in this article, GAAFETs still need to overcome a series of daunting challenges in mass production, including precision metrology, materials innovation, and yield enhancement. This requires concerted efforts and continuous innovation from companies across the global semiconductor supply chain and academic research institutions, along with massive R&D investments, to conquer one technical hurdle after another.

Despite the numerous challenges, the immense potential carried by GAAFETs and their profound impact on key technology areas such as artificial intelligence, high-performance computing, and mobile communications make them a fiercely contested field. We have reason to believe that as these challenges are gradually overcome, GAAFET technology will inevitably lead the semiconductor industry into a new era, continuously driving the digital transformation of human society, and ultimately bringing more powerful and intelligent technological achievements into our lives. GAAFET is not only the crystallization of engineering wisdom but also the key to unlocking infinite possibilities for the future.