Backside Power Delivery: Crossing the 2nm Barrier and Reshaping Chip Performance

Prologue — The Interconnect Bottleneck: Moore's Law's Final Wall

As transistor scaling approaches its physical limits, the primary obstacle to continuing Moore's Law is no longer the transistor itself, but the intricate web of "interconnects" that covers the chip. For decades, the industry has focused on shrinking transistors to pack more of them into a finite area. However, the network of wires responsible for supplying power and transmitting signals to these tens of billions of transistors has evolved into an epic traffic jam.

In current chip designs, power and signal lines are forced to compete for space within the same multi-layered metal structure on the front side of the wafer, creating a fundamental conflict. To reduce resistance and voltage drop (IR Drop), power lines need to be as wide as possible; to pursue speed and density, signal lines must be as thin and tightly packed as possible. This battle for limited routing real estate has become the key bottleneck limiting chip performance and power efficiency. In advanced processes, power-related interconnects can consume over 20% of the routing resources, leading to severe routing congestion.   

Enter the Backside Power Delivery Network (BSPDN). This technology is not merely an incremental process improvement but a complete architectural paradigm shift. It relocates the entire Power Delivery Network (PDN) from the crowded front side to the wafer's backside—previously just a supporting substrate—thereby completely separating power and signal routing and resolving their resource conflict at its root. Its significance is comparable to the introduction of copper interconnects in 1997 and the historic transition from planar transistors to FinFETs.   

This revolution signifies that the driving force of innovation in the semiconductor industry is shifting from "Dimensional Scaling"—making components smaller—to the more complex "Architectural Scaling"—arranging components more intelligently. As wires are scaled to their physical limits, their resistance increases exponentially, causing severe power loss and performance degradation. Simply shrinking dimensions is no longer sustainable. BSPDN is the revolutionary answer to this dilemma. It doesn't try to shrink the wires; instead, it redeploys the entire power grid to an undeveloped territory: the wafer's backside. This strategic pivot will define the trajectory of high-performance computing for the next decade.   

A Technical Deep Dive: Deconstructing the Principles and Challenges of Backside Power Delivery

The Physical Limits of Power Integrity

In a traditional Front-side Power Delivery Network (FSPDN) architecture, current must travel from the package bumps, through layers of increasingly narrow metal wires, to reach the transistors in the core. As transistor density continues to soar, this long power delivery path creates two severe physical challenges:

• IR Drop: According to Ohm's Law (V=I×R), voltage drop is proportional to current (I) and resistance (R). In advanced processes, billions of transistors switching simultaneously generate massive instantaneous currents, while the resistance of scaled-down wires rises sharply. The product of these two factors leads to a significant voltage drop. This means transistors located in the center of the chip, farthest from the power source, receive a much lower voltage than those at the edge, causing them to switch slower, creating performance variability, and even risking logic errors. Chip designers must strive to keep this voltage drop within a 10% tolerance, a task that has become monumental at the 2nm node and below.   

  
  

• Routing Congestion: To mitigate IR Drop, designers are forced to lay wide power and ground rails in the bottom metal layers of the back-end-of-line (BEOL). These wide metal lines act as roadblocks, severely squeezing the available space for signal lines and forcing them to take longer, more convoluted paths. This not only increases signal propagation delay (RC Delay) but also elevates the risk of crosstalk between signals, further degrading chip performance.   

  
  

Architectural Reinvention: The BSPDN Manufacturing Flow

The core concept of BSPDN is to transform the chip into a true three-dimensional structure. Its manufacturing process is exceedingly complex and places unprecedented demands on process integration capabilities. The entire flow inverts the traditional wafer fabrication sequence:

1. Front-side Process Completion: First, all transistors (e.g., Gate-All-Around, or GAA, structures) and the multi-layer metal interconnects for signal routing are fabricated on the front side of the wafer.   

   
   

2. Wafer Flipping and Bonding: The completed front-side wafer is flipped and bonded to a temporary "carrier wafer," which provides mechanical support for the subsequent backside processing. The alignment precision in this step is critical; any minute deviation could result in the entire wafer being scrapped.   

   
   

3. Extreme Wafer Thinning: Next, the original silicon substrate undergoes precise mechanical grinding and chemical etching, reducing its thickness from hundreds of microns to an extreme thinness, often less than 10 microns, and in some schemes, even below 500 nanometers. This process makes the wafer incredibly fragile and susceptible to warpage or cracking, demanding exceptional stress control.   

   
   

4. Backside Processing: With the backside of the transistors fully exposed, backside processing begins. First, nano-Through Silicon Vias (nTSVs) are etched. These vertical channels serve as the bridge connecting the front-side transistors to the backside power grid. Subsequently, a new, dedicated metal network is deposited on the wafer's backside. This network uses wider, thicker wires to form a low-resistance, dedicated power delivery layer, completing the construction of the BSPDN.   

   
   

Implementation Trade-offs: BPR vs. Direct Contact

On the critical question of how to precisely deliver power from the backside to the front-side transistors, two mainstream technical paths have emerged, reflecting the different manufacturing philosophies of various companies:

• Buried Power Rail (BPR): Pioneered by imec, the BPR approach adopts a more modular strategy. Before the transistors are even fabricated, a metal power rail is "buried" in the shallow trench isolation of the silicon wafer. After wafer thinning and backside processing are complete, the backside nTSVs only need to connect to this pre-positioned BPR.   

  
  

  • Advantages: Facilitates more aggressive scaling of standard cell height.
    

  • Challenges: The metal used for the BPR (such as tungsten or ruthenium) must withstand the high temperatures of subsequent transistor fabrication processes, which limits material choices. Additionally, introducing metal in the front-end process carries a risk of contaminating the high-purity silicon.   

    
    

• Direct Backside Contact: Championed by Intel's PowerVia technology, this approach takes a more aggressive and highly integrated design. It completely omits the BPR. Instead, during the front-end process, a "deep via" is etched directly downward from the transistor contact point into the silicon substrate. After the wafer is flipped and thinned, the bottom of these deep vias is naturally exposed on the backside, creating a relatively large "landing pad." The backside metal layers then simply connect to these pads.   

  
  

  • Advantages: Intel claims this is a "self-aligned" process. The larger landing pad area significantly relaxes the stringent alignment accuracy required for the backside metal patterning. This is crucial for overcoming wafer warpage and distortion from bonding, potentially improving yield and reducing costs. It also avoids the contamination risks associated with introducing BPR metal in the front-end and provides a shorter, more direct, low-resistance power path.   

    
    

  • Challenges: Requires the integration of more complex deep via etching technology in the front-end process.

Quantifiable Benefits

The benefits of BSPDN are comprehensive and significant, covering all three core metrics of Power, Performance, and Area (PPA):

• IR Drop Improvement: This is the most direct and dramatic benefit. A collaboration between imec and Arm demonstrated that a BSPDN architecture with BPRs could reduce IR drop by a staggering 7-fold. Other research indicates an IR drop reduction of up to 85%. The fundamental reason is that the current path shifts from a long, narrow front-side route to a short, wide, low-resistance backside shortcut, drastically improving power delivery efficiency.   

  
  

• Performance and Power Gains: Intel claims its PowerVia technology alone delivers a 6% performance boost and a 30% reduction in resistance , with its test chip demonstrating a 5% frequency gain. TSMC's A16 process, featuring BSPDN, targets an 8-10% speed improvement or a 15-20% power reduction at the same speed compared to its N2P node without the technology. Samsung claims its BSPDN technology can deliver an 8% performance gain and a 15% improvement in power efficiency.   

  
  

• Area and Density Scaling: By removing power rails from the front side, BSPDN frees up valuable real estate for logic cells, enabling a 20% to 30% reduction in standard cell area—a benefit equivalent to two generations of lithography advancement. Samsung has specified that introducing BSPDN in its 2nm process will achieve a 17% chip size reduction.   

  
  

The Foundry Triumvirate's Duel: BSPDN Strategies and Technological Showdowns

As BSPDN becomes the decisive factor for the sub-2nm generation, the world's top three foundries—Intel, TSMC, and Samsung—have entered a fierce race for future technology leadership centered on this technology. Their strategies, technical paths, and implementation timelines differ, clearly reflecting their distinct market positions and strategic considerations.

Intel's PowerVia: The Bold Pioneer

Intel sees BSPDN as the core weapon in its quest to reclaim the throne of semiconductor process technology. By being the first to introduce its PowerVia technology in the Intel 20A and 18A nodes between 2024 and 2025, Intel aims to create a significant performance advantage that competitors cannot match for one to two years. This is a high-risk, high-reward strategy reminiscent of Intel's past boldness in launching innovations like High-K Metal Gate and FinFETs.   

Research from market analysis firm TechInsights suggests that Intel 18A holds a performance lead over TSMC's initial N2 node. Intel's own data shows that PowerVia can deliver over a 30% improvement in voltage droop and a 5-6% frequency boost. Intel is positioning 18A as a node focused on extreme performance, a stark contrast to TSMC's initial N2 strategy, which prioritizes density. This directly targets the lucrative High-Performance Computing (HPC) and Artificial Intelligence (AI) markets. Successfully attracting a heavyweight client like Microsoft to adopt the 18A process is a powerful endorsement of its leadership strategy.   

TSMC's Super Power Rail: The Steady Incumbent

As the market leader, TSMC has adopted a more cautious, ecosystem-centric evolutionary strategy. TSMC has named its BSPDN technology "Super Power Rail" and plans to officially introduce it in its A16 node (1.6nm-class) in 2026, following its initial N2 and performance-enhanced N2P nodes.   

This phased approach allows the entire semiconductor ecosystem—including customers, EDA tool vendors, and IP design houses—to first adapt to the new GAA transistor architecture on the N2 node before layering on the added complexity of BSPDN. This tiered product roadmap offers customers diverse options: mobile clients like Apple can prioritize N2 for the highest transistor density; customers needing higher performance can choose N2P, which is based on a mature GAA process; and top-tier HPC/AI clients like Nvidia, who seek the ultimate PPA, can wait for the more technologically comprehensive A16. This strategy minimizes technology adoption risks. According to TSMC's plan, A16 is expected to deliver an 8-10% speed improvement or a 15-20% power reduction compared to N2P, along with up to a 1.10x chip density gain.   

Samsung's SF2Z: The Determined Challenger

Samsung Electronics is in the position of a challenger in the BSPDN race, with its BSPDN-equipped SF2Z node scheduled for mass production in 2027. Despite the later timeline, Samsung is attempting to win over customers by proposing highly attractive PPA gains. Samsung has publicly stated that its BSPDN technology will achieve a 17% chip size reduction, an 8% performance boost, and a 15% power efficiency improvement compared to a traditional front-side power 2nm chip.   

However, Samsung's main challenge lies not just in its technological claims but in its execution of mass production. Although Samsung was the first in the world to introduce the GAA architecture at the 3nm node, it faced initial challenges with yield and customer adoption. Therefore, Samsung must prove to the market that it can mass-produce the more complex BSPDN technology with competitive yield and cost by 2027. This will be key to winning customer trust.   

BSPDN Technology Comparison of Major Foundries

Foundry	Technology Name	Node	Transistor Architecture	Est. Mass Production	Claimed Benefits (vs. non-BSPDN node)
Intel	PowerVia	Intel 20A / 18A	RibbonFET (GAA)	2024 H2 / 2025 H2	5-6% speed increase, 30% voltage droop improvement
TSMC	Super Power Rail	A16	Nanosheet (GAA)	2026 H2	8-10% speed increase, 15-20% power reduction, up to 1.10x density gain
Samsung	BSPDN	SF2Z	GAA	2027	8% speed increase, 15% power reduction, 17% area reduction

Behind this race is not just a choice of technical routes, but a reflection of business models and risk tolerance. Intel, as a challenger seeking a revival, must bear the risks of being a technology leader to attract customers with a unique advantage. TSMC, as the market defender, prioritizes ecosystem stability and predictable execution. And Samsung is attempting to use significant PPA improvements as a bargaining chip to achieve a late-mover advantage. The outcome of this technological gamble will profoundly impact the competitive landscape of the global semiconductor industry for years to come.

A Paradigm Shift in Design: The Impact of BSPDN on EDA Tools and IC Design

The introduction of BSPDN is not just a manufacturing revolution; it brings disruptive changes to the upstream Integrated Circuit (IC) design flow and Electronic Design Automation (EDA) tools. For decades, the entire design flow, from RTL to GDSII, has been built on a fundamental assumption: all routing layers are on the front side of the wafer. The advent of BSPDN shatters this assumption, forcing the entire design ecosystem to undergo a bottom-up overhaul.   

The EDA Tool Revolution

Existing EDA tools cannot handle a 3D power grid that exists on both the front and back sides of a wafer, creating an urgent need for a new generation of design tools:

• Place & Route: Traditional placement and routing algorithms must be rewritten to simultaneously consider the layout of front-side signal lines and backside power lines. Placement tools need to learn how to intelligently insert special nTSV cells to connect to the backside grid, especially during the transition period when legacy standard cell libraries are still in use.   

  
  

• Power Analysis: Analysis engines for IR Drop and Electromigration must be completely re-architected. They need to accurately model the complex 3D path of current flowing from the backside grid, through nTSVs, to the front-side transistors, and calculate the voltage loss and physical stress along the way.   

  
  

• Extraction: Extraction engines must be upgraded to accurately calculate the parasitic resistance and capacitance generated by the backside metal layers and nTSV structures. The accuracy of these parameters directly impacts the results of chip timing and power analysis.   

  
  

• Thermal Analysis: Thermal management has become a core issue like never before. New EDA tools must have multi-physics simulation capabilities to simultaneously model heat conduction on both the front and back sides of the chip. Because the material structures and heat dissipation paths on the front and back are drastically different, the complexity of thermal analysis increases exponentially.   

  
  

New Design Challenges

For IC design teams, BSPDN brings new challenges and design considerations:

• Redesign of Standard Cell Libraries: The standard cell libraries widely used in the industry today have their power rails designed on the front-side metal layers, making them completely incompatible with the BSPDN architecture. The entire industry needs to invest enormous time and resources to develop and validate new standard cell libraries specifically designed for backside power, a monumental undertaking.   

  
  

• The Thermal Management Nightmare: A key and counter-intuitive challenge is that while BSPDN improves electrical performance, it can worsen the chip's thermal performance. In traditional designs, the multi-layer metal grid on the front side also plays a role in evenly dissipating heat. Moving this massive metal structure to the back effectively removes a major heat dissipation pathway. Furthermore, with the freed-up routing space, transistors can be packed more densely, further increasing power density per unit area. Heat must now be primarily extracted from the backside, which not only requires the chip to be packaged in a flip-chip configuration but also drives the need for entirely new thermal solutions.   

  
  

• The Signal Shielding Dilemma: For a long time, designers have used the front-side power and ground grid for shielding sensitive analog circuits or high-speed signal lines to prevent noise interference. With the power grid moved to the backside, finding a stable and convenient voltage reference point on the front side for shielding lines has become a tricky new signal integrity problem.   

  
  

This transformation triggered by BSPDN has temporarily created a "chasm" in the design ecosystem. Foundries are actively developing the manufacturing technology, but the EDA tools and IP cores that can effectively utilize these technologies are lagging. This presents high costs and risks for early adopters. In this context, a foundry's competitiveness depends not only on its manufacturing capabilities but also on its ability to manage and nurture its design ecosystem. The one who can better collaborate with EDA partners to provide customers with a more mature, lower-risk design flow is more likely to win in this generational shift.

Synergy: The Integration of Gate-All-Around (GAA) Architecture and BSPDN

At the sub-2nm advanced nodes, BSPDN is not an isolated technological innovation. It is closely linked and complementary to another key transistor architecture change—Gate-All-Around (GAA). The synergy between these two technologies forms the dual engines driving the semiconductor industry into the Angstrom era.

The Necessity of GAA

The evolution from planar transistors to FinFETs, and now to GAA, is a necessary progression for transistor structures to overcome physical limits. As the channel length of transistors shrinks to the extreme, the three-sided gate structure of traditional FinFETs can no longer fully suppress current leakage. The GAA architecture, typically implemented in the form of nanosheets, allows the gate to completely wrap around the channel from all four sides, providing superior electrostatic control. This enables lower power consumption and higher performance at smaller dimensions. Consequently, Intel, TSMC, and Samsung have all adopted GAA as the core transistor architecture in their 2nm-class process roadmaps.   

Unleashing the Full Potential of GAA

GAA and BSPDN are a highly synergistic technology pair. The GAA architecture allows for denser transistor stacking and creates the conditions for further scaling of standard cell height (e.g., reducing from the traditional 6-track to 5-track). However, without sufficient routing space to connect these high-density logic cells, the density advantage brought by GAA would be unrealized.

BSPDN provides the much-needed "breathing room" for high-density GAA designs. By moving the area-consuming power rails to the wafer's backside, it frees up all the front-side routing tracks to be dedicated to the complex signal network connecting the GAA transistors. It can be said that without BSPDN to solve the routing congestion problem, the high-density advantage of GAA would be nullified by the interconnect bottleneck.   

A New Manufacturing Hurdle: Mechanical Stress

However, the integration of these two cutting-edge technologies also introduces a hidden but severe manufacturing challenge: the management of mechanical stress. The complex manufacturing process of BSPDN, especially wafer thinning, bonding to a carrier wafer, and the deposition of backside metal layers, introduces significant physical stress across the entire wafer. The mismatch in thermal expansion coefficients between different materials can cause minute deformations and strains in the wafer during processing.   

This stress is directly transferred to the finely structured GAA nanosheet channels on the front side of the wafer. Because nanosheets are suspended structures, they are extremely sensitive to external stress. A change in stress can directly affect the silicon lattice structure, thereby altering the carrier mobility of electrons and holes in the channel, and ultimately impacting the transistor's switching speed and reliability in unpredictable ways. Analysis from equipment vendors like Lam Research confirms that backside connection schemes indeed generate greater mechanical stress in the transistor channel compared to traditional front-side schemes, making stress management one of the top challenges in process integration.   

This means that the success of the 2nm node depends on a deep "co-optimization" of GAA transistor performance and the BSPDN manufacturing process. Foundries can no longer consider the front-end (transistor fabrication) and back-end (backside power) processes separately. Any adjustment in the backside process that seems beneficial could have unintended negative consequences on the front-side transistor characteristics. Therefore, foundries must use advanced Technology Computer-Aided Design (TCAD) tools to conduct comprehensive simulations of the entire system's electrical, thermal, and mechanical multi-physics effects. The foundry that can first master this complex interplay—maximizing the electrical benefits of BSPDN while minimizing its negative stress impact on GAA transistors—will achieve ultimate victory in yield and performance. This is the invisible battle line, fought beneath the surface, that will determine future success.

Conclusion — Powering the Angstrom Era: The Strategic Significance and Future of BSPDN

In summary, the Backside Power Delivery Network (BSPDN) is not an optional feature but an indispensable foundational technology driving the semiconductor industry into the Angstrom era. It provides the most critical and, to date, most effective solution to the interconnect bottleneck that has long plagued Moore's Law.

The robust and stable power delivery capability of BSPDN precisely meets the immense power demands of next-generation AI accelerators and high-performance computing processors. It is foreseeable that this technology will become the core engine supporting the continued growth of these disruptive applications. Consequently, the race to mass-produce BSPDN has become the most decisive battleground in the foundry landscape for the next five years. Intel's aggressive deployment of PowerVia is an attempt to disrupt the existing market structure, and its success or failure will profoundly impact the future of its foundry services. Meanwhile, TSMC's steady advancement with A16 demonstrates its mature control over technological risk and ecosystem stability as the market leader.   

On a more profound level, BSPDN paves the way for the era of true three-dimensional chip integration. The key technologies accumulated in the process of realizing BSPDN—such as extreme wafer thinning, high-precision wafer bonding, and complex backside processing capabilities—will be the cornerstones for achieving more advanced architectures in the future. These technologies will be directly applicable to Complementary FETs (CFETs), which stack N-type and P-type transistors vertically, and to more complex Wafer-on-Wafer 3D stacking technologies.   

The backside of the wafer is no longer just a substrate carrying the glory of the front side; it has become the next frontier of semiconductor innovation. The successful implementation of BSPDN will fundamentally change how chips are designed and manufactured, injecting new vitality into the economic benefits of Moore's Law and laying the most solid physical foundation for a future driven by AI and ubiquitous computing.